Design Integrity Status Report

Report Written: Thursday, February 20, 2025
Design Path: G:\Independent_Project\Simulations\Tracking_Device\Easy-PC\Easy-PC\LoRa_Device.pcb
Design Title:  
Created: 19/02/2025 15:28:45
Last Saved: 20/02/2025 19:47:55
Editing Time: 517 min
Units: mm (precision 1)

Checking integrity of Schematic "G:\Independent_Project\Simulations\Tracking_Device\Easy-PC\Easy-PC\LoRa_Device.sch" with PCB "G:\Independent_Project\Simulations\Tracking_Device\Easy-PC\Easy-PC\LoRa_Device.pcb"

End Of Report.